Updated PT, modified V and added VT. #1

iihihiuh · 2019-04-29T18:20:08Z

Change mtime, mtimecmp csr accesses to memory mapped loads and stores. Added env VT(virtual timer interrupt)

farzamgl

Good changes! Fixes the problem of limited(2MB) user space.
Can we not change the v/* files for now though? I'm still working on debugging with the current version.

farzamgl · 2019-04-29T19:00:03Z

encoding.h

 #define PTE_PPN_SHIFT 10
+#define PTE_PPN_OFFST 2


I think most of these constants can already be found in the header files

OK. I will look into it to find some replacement

farzamgl · 2019-04-29T19:13:22Z

v/vm.c

+    // creating new page                                                                                               
+    // get a new page from global ppgdir                                                                                
+    uint64_t newPage = alloc();
+    pt[0][VPN2(vaddr)] = ((newPage & ~0xfff) >> PTE_PPN_OFFST) | PTE_V;


the newpage's address should be asserted to be aligned with 4K pages instead of clearing the lower 12 bits.

farzamgl · 2019-04-29T19:19:34Z

v/vm.c

@@ -296,5 +364,13 @@ void vm_boot(uintptr_t test_addr)
  trapframe_t tf;
  memset(&tf, 0, sizeof(tf));
  tf.epc = test_addr - DRAM_BASE;
+
+  //user_llpt[VPN0(tf.epc)] = ((pte_t)test_addr/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
+  for (long i = 0; i < usize; i++)


Before these changes, the user pages were not actually in the same location as the physical pages in the mem.
And on a page-fault, it copied those physical pages to the allocated user addresses.
I am not sure if one approach is better than the other, but in the old one, user mappings can be random and independent of how the code is loaded in the mem.

Certainly original way will allow us to test page fault.

dpetrisko · 2019-04-29T19:39:11Z

encoding.h

@@ -166,11 +167,19 @@
 #define PTE_A     0x040 // Accessed
 #define PTE_D     0x080 // Dirty
 #define PTE_SOFT  0x300 // Reserved for Software
-
+#define PTE_PPN 0x3ffffffffffc00


Why is the PPN constant?

This is a mask to extract physical page number from pte entry,

Oh, give it a name that indicates that it’s a mask

dpetrisko · 2019-04-29T19:41:23Z

v/vm.c

+    freelist_head = freelist_tail = 0;
+  return res;
+}
+


These seem like substantial changes to how the VM works. @farzamgl is all this necessary to support the 2MB userspace?

This code generalizes the page-table generation so we can have more than 2MB space. It's not that different except the way that the mappings are done, and there is no page copying.
In the original code, there is only 1 entry in L2 page-table for each user and kernel code.

In the vt/*, there will be user code copying and remapping when a timer interrupt is taken.

dpetrisko · 2019-04-29T19:42:06Z

v/vm.c

+  pte_t* second_pte_ptr;
+  pte_t second_pte;
+  pte_t* third_pte_ptr;
+  pte_t third_pte;


You don't need separate ptr variables, just use & operator

& operator on local variables does not return address to original page table. To modify original pte value, I belive a pointer is necessary.

You can go the reverse way if necessary. The point is you don’t need a variable for both the pointer and the pointer contents

Sure. Your way is cleaner

iihihiuh

@farzamgl Yes, I will leave v/* unchanged and put all my changes into vt/*.

vt/* utilizes timer interrupts to make remapping more frequent.

dpetrisko · 2019-04-29T19:43:50Z

pt/riscv_test.h

-        addi a0, a0, TIMER_INTERVAL;                                    \
-        csrw mtimecmp, a0;                                              \
+	csrr t0, mstatus;						\
+	ori t0, t0, MSTATUS_MPIE;					\


Why are you changing PIE here?

on mret. mie in mstatus will become mpie in mstatus. mie in mstatus is the global interrupt enable signal.

That’s done in hardware

Yes. If I do not write MPIE before mret, MIE will be clearer after mret.

No it won’t. On the timer interrupt, MPIE becomes MIE (1) in hardware. On MRET, MIE becomes MPIE (1)

Because on MRET, MIE becomes MPIE. I write MPIE to 1 to before MRET to enable timer interrupt after MRE.

You’re not understanding. MPIE is already 1 when you’re in the trap. If it weren’t, you wouldn’t have taken the trap

Look at how the old spike code worked. They didn’t need to write to MPIE

This MPIE is only for initialization. During reset mstatus was all zeros.

farzamgl

revert v/* to the version on blackparrot_mods not master

dpetrisko and others added 9 commits April 23, 2019 18:44

Adding blackparrot termination conditions

0d85d04

changed V env to use M mode instead of S

24cf46c

added fake ufinish CSR for simulation end

1c0b36c

Adding link to our mtvec handler

1423706

Simplifying termination condition

0a3d6bc

functions incorporated

1a8e080

start point

14428d0

timer environment add

79cb643

macro applyed

2109241

iihihiuh self-assigned this Apr 29, 2019

iihihiuh requested a review from dpetrisko April 29, 2019 18:21

farzamgl reviewed Apr 29, 2019

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dpetrisko reviewed Apr 29, 2019

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iihihiuh commented Apr 29, 2019

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dpetrisko reviewed Apr 29, 2019

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yongqw added 3 commits April 29, 2019 13:53

revert v

27542f1

macro name changed unncessary constant removed

e6a8f25

backup file removed

37fde77

farzamgl requested changes Apr 29, 2019

View reviewed changes

v in bp_mode recovered

46293c3

farzamgl approved these changes Apr 29, 2019

View reviewed changes

dpetrisko force-pushed the blackparrot_mods branch from c49a9a0 to d8f777c Compare November 23, 2019 14:01

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Updated PT, modified V and added VT. #1

Updated PT, modified V and added VT. #1

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Updated PT, modified V and added VT. #1

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Updated PT, modified V and added VT. #1

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